The present invention generally relates to data processing systems and more particularly relates to apparatus by which asynchronous transfers of information are synchronized.
In data processing systems, clock signals are utilized to strobe information into and out of various registers, arithmetric elements and the like which are included in the system. Data may be transferred between such elements and registers in a synchronous manner wherein transfers are only allowed at a specified time, i.e., at the time a clock pulse of a stream of repetitive clock pulses is present. In some systems, various transfers are provided in an asynchronous manner with the data so transferred not utilized until the system has ensured that such data has been so transferred and received. Some such systems include means for transferring a synchronizing clock pulse with the data so as to provide the synchronization required. Further systems provide a clock system by which synchronization is completed but only upon the occurrence of one of a plurality of clock pulses which are synchronous in nature and are not adaptive to the asynchronous transfer of information. That is to say, although the information is transferred in an asynchronous manner, the information cannot be so utilized in the system until a clock pulse has been so generated. In some instances wherein for example the data has been received just after a clock pulse has been generated, much time is wasted in synchronizing such data since it is not made available for use until the occurrence of the next clock pulse.
It is accordingly a primary object of the invention to provide apparatus for synchronizing the asynchronous transfer of information over a bus coupling a plurality of units in a data processing system including a stalling mechanism by which the synchronizing clock pulses may be delayed in order to adapt for the asynchronous transfers.